Communications of the ACM
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Simple Circuits that Work for Complicated Reasons
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Multiple-Rail Phase-Encoding for NoC
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
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A radical approach to high-speed on-chip communication between computational modules is proposed. Data communication is performed over multiple serial buses, where the time difference between events is used to encode and decode data on a number of wires. We present results obtained through a proof-of-concept implementation on FPGA and simulations on a 0.18\mu m technology.