NoC Communication Strategies Using Time-to-Digital Conversion
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS
WSEAS Transactions on Computers
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing
Microprocessors & Microsystems
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We present a novel approach to long-wire signalling. We use the traditional division of long wires into buffered segments, but the delay of each buffer is modulated by signals derived from a timing chain. This creates a circuit element whose timing behaviour is between that of an inverter and that of a latch. We call these "soft latches". We demonstrate the advantages of our approach by comparing it with synchronous and asynchronous interconnect pipelining. We present results from HSPICE simulations to evaluate the robustness of our circuits.