Electromigration: the time bomb in deep-submicron ICs
IEEE Spectrum
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-Speed Clock Network Design
High-Speed Clock Network Design
Power Distribution Network Design for VLSI
Power Distribution Network Design for VLSI
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This paper describes power grid planning methodology for high-performance microprocessors and SOC chips. It shows how to estimate currents from an existing chip to a new chip. The power grid planning and pre-layout simulation becomes important for time to market of chip design. We will discuss the current scaling technique and one SOC design example. More details on the methodology can be found in [Power Distribution Network Design for VLSI].