Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimized design of parallel carry-select adders
Integration, the VLSI Journal
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In this paper we address the problem of adding two n-bit numbers when the bit arrival times are arbitrary (but known in advance). In particular we address a simplified version of the problem where the input arrival times for the i/sup th/ significant bits of both addends are the same, and the arrival times t/sub i/ have a profile of the form: t/sub 0//spl les/t/sub 1//spl les/.../spl les/t/sub k/=t/sub k+1/=...=t/sub p/t/sub p+1//spl ges/.../spl ges/t/sub n-1/. This profile is important because it matches the signal arrival time profile of the reduced partial products in a parallel multiplier before they are summed in the final adder. In this paper we present a design strategy specific to arrival time profiles generated by partial product reduction trees constructed by optimal application of the Three Dimensional Method presented by V.G. Oklobdzija et al. (1995). This strategy can be used to obtain adders for any arrival time profile that matches the above form, as well as a broad class of arrival time profiles where even greater variation in the input times is allowed. Finally, we show that our designs significantly outperform the standard adder designs for the uniform signal arrival profile, yielding faster adders that (for these profiles) are also simpler and use fewer gates.