Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
Design strategies for the final adder in a parallel multiplier
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Low-power carry-select adder using adaptive supply voltage based on input vector patterns
Proceedings of the 2004 international symposium on Low power electronics and design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
High-Performance Carry Select Adder Using Fast All-One Finding Logic
AMS '08 Proceedings of the 2008 Second Asia International Conference on Modelling & Simulation (AMS)
M*N Booth encoded multiplier generator using optimized Wallace trees
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
In this paper, a novel gate-level strategy for designing Carry-Select adders is proposed. The strategy is more general than the previously proposed techniques, and accounts for the dependence of multiplexer delay on its fan-out. Moreover the strategy is simple and systematic, and is helpful for designing Carry-Select adders with a pencil-and-paper approach. An approximate expression of the minimum delay achievable is derived to estimate performance before carrying out the design. The proposed strategy is validated in more than 1000 adders. Analysis confirms that the strategy leads to a delay which is minimal in most cases, and always within 5.7%.