Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Parallel computing using the prefix problem
Parallel computing using the prefix problem
Using MPI: portable parallel programming with the message-passing interface
Using MPI: portable parallel programming with the message-passing interface
The communication software and parallel environment of the IBM SP2
IBM Systems Journal
Parallel prefix computation on a pyramid computer
Pattern Recognition Letters
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
IEEE Transactions on Computers
Parallel computation: models and methods
Parallel computation: models and methods
Asynchronous Parallel Prefix Computation
IEEE Transactions on Computers
Finding optimal parallel prefix circuits with fan-out 2 in constant time
Information Processing Letters
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
Efficient parallel prefix algorithms on mulitport message-passing systems
Information Processing Letters
Computing Moments by Prefix Sums
Journal of VLSI Signal Processing Systems
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
Prefix computations on symmetric multiprocessors
Journal of Parallel and Distributed Computing
Optimal and efficient algorithms for summing and prefix summing on parallel machines
Journal of Parallel and Distributed Computing
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
Modeling Communication Overhead: MPI and MPL Performance on the IBM SP2
IEEE Parallel & Distributed Technology: Systems & Technology
Parallel complexity of the medial axis computation
ICIP '95 Proceedings of the 1995 International Conference on Image Processing (Vol.2)-Volume 2 - Volume 2
Parallel biological sequence comparison using prefix computations
Journal of Parallel and Distributed Computing
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System
The Journal of Supercomputing
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
O(log*n) algorithms on a Sum-CRCW PRAM
Computing
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
New families of computation-efficient parallel prefix algorithms
WSEAS Transactions on Computers
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Two families of computation-efficient parallel prefix algorithms for message-passing multicomputers are presented. The first family generalizes previous algorithms that use only half-duplex communications and thus can improve the running time. The second adopts collective communication operations to reduce the communication time. The proposed algorithms have the shortest computation time of all prefix algorithms for the multicomputer models. The precondition of the proposed algorithms is also derived. These families provide the flexibility of choosing either less computation time or less communication time to achieve the minimal running time.