Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System

  • Authors:

  • Amitava Datta

  • Affiliations:

  • School of Computer Science & Software Engineering, The University of Western Australia, Perth, WA 6009, Australia. datta@csse.uwa.edu.au

  • Venue:
  • The Journal of Supercomputing
  • Year:
  • 2004

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Abstract

We present several fast algorithms for multiple addition and prefix sum on the Linear Array with a Reconfigurable Pipelined Bus System (LARPBS), a recently proposed architecture based on optical buses. Our algorithm for adding N integers runs on an N log M-processor LARPBS in O(log* N) time, where log* N is the number of times logarithm has to be taken to reduce N below 1 and M is the largest integer in the input. Our addition algorithm improves the time complexity of several matrix multiplication algorithms proposed by Li, Pan and Zheng (IEEE Trans. Parallel and Distributed Systems, 9(8):705–720, 1998). We also present several fast algorithms for computing prefix sums of N integers on the LARPBS. For integers with bounded magnitude, our first algorithm for prefix sum computation runs in O(log log N) time using N processors and in O(1) time using N1+ϵ processors, for \frac{1}{3} ≤ ϵ O(log log N log* N) time using N log M processors, when M is the largest integer in the input. Our second algorithm for multiple addition runs in O(log* N) time using N1+ϵ log M processors, for \frac {1}{3} ≤ ϵ