A Heuristic for Suffix Solutions
IEEE Transactions on Computers
Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
Faster optimal parallel prefix sums and list ranking
Information and Computation
Scans as Primitive Parallel Operations
IEEE Transactions on Computers
Limited width parallel prefix circuits
The Journal of Supercomputing
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
SIAM Journal on Computing
Parallelizing complex scans and reductions
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Parallel computing using the prefix problem
Parallel computing using the prefix problem
Using MPI: portable parallel programming with the message-passing interface
Using MPI: portable parallel programming with the message-passing interface
The communication software and parallel environment of the IBM SP2
IBM Systems Journal
Parallel prefix computation on a pyramid computer
Pattern Recognition Letters
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
IEEE Transactions on Computers
Parallel computation: models and methods
Parallel computation: models and methods
Asynchronous Parallel Prefix Computation
IEEE Transactions on Computers
Finding optimal parallel prefix circuits with fan-out 2 in constant time
Information Processing Letters
Journal of the ACM (JACM)
A New Class of Depth-Size Optimal Parallel Prefix Circuits
The Journal of Supercomputing
Efficient parallel prefix algorithms on mulitport message-passing systems
Information Processing Letters
Computing Moments by Prefix Sums
Journal of VLSI Signal Processing Systems
Scalable Hardware-Algorithms for Binary Prefix Sums
IEEE Transactions on Parallel and Distributed Systems
Prefix computations on symmetric multiprocessors
Journal of Parallel and Distributed Computing
Optimal and efficient algorithms for summing and prefix summing on parallel machines
Journal of Parallel and Distributed Computing
Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit
The Journal of Supercomputing
Modeling Communication Overhead: MPI and MPL Performance on the IBM SP2
IEEE Parallel & Distributed Technology: Systems & Technology
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
Parallel complexity of the medial axis computation
ICIP '95 Proceedings of the 1995 International Conference on Image Processing (Vol.2)-Volume 2 - Volume 2
Parallel biological sequence comparison using prefix computations
Journal of Parallel and Distributed Computing
Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
A new approach to constructing optimal parallel prefix circuits with small depth
Journal of Parallel and Distributed Computing
Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System
The Journal of Supercomputing
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast Parallel-Prefix Modulo 2^n+1 Adders
IEEE Transactions on Computers
Faster optimal parallel prefix circuits: New algorithmic construction
Journal of Parallel and Distributed Computing
On the construction of zero-deficiency parallel prefix circuits with minimum depth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
O(log*n) algorithms on a Sum-CRCW PRAM
Computing
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Reconfigurable hardware solution to parallel prefix computation
The Journal of Supercomputing
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel prefix algorithms on the multicomputer
WSEAS Transactions on Computer Research
Fast problem-size-independent parallel prefix circuits
Journal of Parallel and Distributed Computing
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New families of computation-efficient parallel prefix algorithms for message-passing multicomputers are presented. The first family improves the communication time of a previous family of parallel prefix algorithms; both use only half-duplex communications. Two other families adopt collective communication operations to reduce the communication times of the former two, respectively. These families each provide the flexibility of either fewer computation time steps or fewer communication time steps to achieve the minimal running time depending on the ratio of the time required by a communication step to the time required by a computation step.