Constructing H4, a Fast Depth-Size Optimal Parallel Prefix Circuit

  • Authors:

  • Yen-Chun Lin;Yao-Hsien Hsu;Chun-Keng Liu

  • Affiliations:

  • Dept. of Computer Science and Information Engineering, National Taiwan University of Science and Technology, P.O. Box 90-100, Taipei 106, Taiwan yclin@computer.org;Dept. of Computer Science and Information Engineering, National Taiwan University of Science and Technology, P.O. Box 90-100, Taipei 106, Taiwan;Dept. of Electronic Engineering, National Taiwan University of Science and Technology, P.O. Box 90-100, Taipei 106, Taiwan

  • Venue:
  • The Journal of Supercomputing
  • Year:
  • 2003

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Abstract

Given n values x1, x2,…,xn and an associative binary operation ⊗, the prefix problem is to compute x1⊗x2⊗⃛⊗xi, 1≤i≤n. Prefix circuits are combinational circuits for solving the prefix problem. For any n-input prefix circuit D with depth d and size s, if d+s=2n−2, then D is depth-size optimal. In general, a prefix circuit with a small depth is faster than one with a large depth. For prefix circuits with the same depth, a prefix circuit with a smaller fan-out occupies less area and is faster in VLSI implementation. This paper is on constructing parallel prefix circuits that are depth-size optimal with small depth and small fan-out. We construct a depth-size optimal prefix circuit H4 with fan-out 4. It has the smallest depth among all known depth-size optimal prefix circuits with a constant fan-out; furthermore, when n≥136, its depth is less than, or equal to, those of all known depth-size optimal prefix circuits with unlimited fan-out. A size lower bound of prefix circuits is also derived. Some properties related to depth-size optimality and size optimality are introduced; they are used to prove that H4 is depth-size optimal.