Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
Journal of the ACM (JACM)
Introduction to VLSI Systems
Lower Bounds for Constant Depth Circuits for Prefix Problems
Proceedings of the 10th Colloquium on Automata, Languages and Programming
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
A model of computation for VLSI with related complexity results
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI
Area-efficient vlsi computation
Area-efficient vlsi computation
Parallel computation using limited resources
Parallel computation using limited resources
Computational Aspects of VLSI
An Algorithmic Approach for Generic Parallel Adders
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Consideration is given to the layout of bounded fan-in and fan-out prefix computation graphs in VLSI, and it is shown that the area requirements of such graphs exhibit this interesting property. A small constant factor reduction in time of computation from 2 log eta to log eta increases the area required to embed an eta node prefix computation graph significantly from O( eta log eta ) to Omega ( eta /sup 2/). The area requirements are also given. This behavior is an example of an extreme area-time tradeoff in VLSI. Since prefix computation also models the carry computation in a carry look-ahead adder, the same behavior is observed in the area requirements of a near-minimum computation time carry look-ahead adder. The authors also present circuits which meet the derived lower bounds for all values of T between log eta and 2 log eta .