Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
Proc. of the Aegean workshop on computing on VLSI algorithms and architectures
Optimal VLSI circuits for sorting
Journal of the ACM (JACM)
Journal of the ACM (JACM)
Structure of Computers and Computations
Structure of Computers and Computations
Lower Bounds for Constant Depth Circuits for Prefix Problems
Proceedings of the 10th Colloquium on Automata, Languages and Programming
The Influence of Key Length on the Area-Time Complexity of Sorting
Proceedings of the 12th Colloquium on Automata, Languages and Programming
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Unbounded fan-in circuits and associative functions
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
The area-time complexity of sorting (algorithms, computation, architecture, vlsi)
Counter-Free Automata (M.I.T. research monograph no. 65)
Counter-Free Automata (M.I.T. research monograph no. 65)
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Deterministic on-line routing on area-universal networks
Journal of the ACM (JACM)
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The average time complexity to compute preffix functions in processor networks
STACS'99 Proceedings of the 16th annual conference on Theoretical aspects of computer science
A bibliography on computational molecular biology and genetics
Mathematical and Computer Modelling: An International Journal
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The prefix problem consists of computing all the products x0x1 … xj (j = 0, … , N - 1), given a sequence x = (x0, x1, … , xN-1) of elements in a semigroup. In this paper we completely characterize the size-time complexity of computing prefixes with Boolean networks, which are synchronized interconnections of Boolean gates and one-bit storage devices. This complexity crucially depends upon two properties of the underlying semigroup, which we call cycle-freedom (no cycle of length greater than one in the Cayley graph of the semigroup), and memory-induciveness (arbitrarily long products of semigroup elements are true functions of all their factors). A nontrivial characterization is given of non-memory-inducive semigroups as those whose recurrent subsemigroup (formed by the elements with self-loops in the Cayley graph) is the direct product of a left-zero semigroup and a right-zero semigroup. Denoting by S and T size and computation time, respectively, we have S = &THgr;((N/T)log(N/T)) for memory-inducive non-cycle-free semigroups, and S = &THgr;(N/T) for all other semigroups. We have T &egr; [&OHgr;(log N), &Ogr;(N)] for all semigroups, with the exception of those whose recurrent subsemigroup is a right-zero semigroup, for which T &egr; [&OHgr;(1), &Ogr;(N)]. The preceding results are also extended to the VLSI model of computation. Area-time optimal circuits are obtained for both boundary and nonboundary I/O protocols.