The second generation motis mixed-mode simulator
DAC '84 Proceedings of the 21st Design Automation Conference
Relax: A new circuit for large scale MOS integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Switch-Level Model and Simulator for MOS Digital Systems
Switch-Level Model and Simulator for MOS Digital Systems
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A constraint based approach to automatic design of analog cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SYNOPA: an automated synthesizer for CMOS operational amplifiers
EURO-DAC '94 Proceedings of the conference on European design automation
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator
EURO-DAC '91 Proceedings of the conference on European design automation
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
EURO-DAC '91 Proceedings of the conference on European design automation
A new approach to layout of custom analog cells
EURO-DAC '91 Proceedings of the conference on European design automation
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A new algorithm for third generation circuit simulators, the “ONE-STEP RELAXATION METHOD” (OSR), as well as a concrete implementation of it, the new circuit simulator ELDO, are presented. This algorithm can replace the NEWTON method used in most second generation circuit simulators. Contrary to “Timing Simulator” algorithms, OSR makes no simplifying hypotheses on weak couplings between nodes. OSR performances are close to those of the “WAVEFORM RELAXATION METHOD” (WRM) used in the recent circuit simulator RELAX. But OSR requires less memory space than the WRM and its CPU-time increases linearly with the interval of simulated time. Eldo has already been used for the accurate simulation of a 1600 MOS digital-analog converter : less than one megabyte memory size was required.