GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Combinational equivalence checking for threshold logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
A fault tolerant threshold logic gate design
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
Scalable identification of threshold logic functions
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Novel universal threshold logic gate based on RTD and its application
Microelectronics Journal
Optimal synthesis of boolean functions by threshold functions
ICANN'06 Proceedings of the 16th international conference on Artificial Neural Networks - Volume Part I
Using kolmogorov inspired gates for low power nanoelectronics
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
A scalable threshold logic synthesis method using ZBDDs
Proceedings of the great lakes symposium on VLSI
An efficient heuristic to identify threshold logic functions
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
Nanopipelined threshold network synthesis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. Many nanotechnologies, such as resonant tunneling diodes, quantum cellular automata, and single electron tunneling, are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionally-correct threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multilevel threshold network synthesis. We have built the first such tool, threshold logic synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, up to 80.0% and 70.6% reduction in gate count and interconnect count, respectively, is possible with the average being 22.7% and 12.6%, respectively. Furthermore, the synthesized networks are well-balanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multilevel threshold logic design.