Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Deeper Sparsely Nets can be Optimal
Neural Processing Letters
Chow Parameters in Threshold Logic
Journal of the ACM (JACM)
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Current-Mode Threshold Logic Gates
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A Threshold Logic Synthesis Tool for RTD Circuits
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
Design Guides for a Correct DC Operation in RTD-based Threshold Gates
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Evaluation and Comparison of Threshold Logic Gates
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
Threshold Gate Approximations Based on Chow Parameters
IEEE Transactions on Computers
Enumeration of Threshold Functions of Eight Variables
IEEE Transactions on Computers
An Algorithm for Testing 2-Asummability of Boolean Functions
IEEE Transactions on Computers
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
STOC '08 Proceedings of the fortieth annual ACM symposium on Theory of computing
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
A fault tolerant threshold logic gate design
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
Operation limits for RTD-based MOBILE circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Scalable identification of threshold logic functions
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Nanopipelined threshold network synthesis
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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A fast method to identify the given Boolean function as a threshold function with weight assignment is introduced. It characterizes the function based on the parameters that have been defined in the literature. The proposed method is capable to quickly characterize all functions that have less than eight inputs and has been shown to operate fast for functions with as many as forty inputs. Furthermore, comparisons with other existing heuristic methods show huge increase in the number of threshold functions identified, and drastic reduction in time and complexity.