Optimal clustering for delay minimization
DAC '93 Proceedings of the 30th international Design Automation Conference
Finding all simple disjunctive decompositions using irredundant sum-of-products forms
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Threshold logic circuit design of parallel adders using resonant tunneling devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
An Algorithm for Testing Asummability of Boolean Functions
IEEE Transactions on Computers
Enumeration of Threshold Functions of Eight Variables
IEEE Transactions on Computers
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Scalable identification of threshold logic functions
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Exploring the Potential of Threshold Logic for Cryptography-Related Operations
IEEE Transactions on Computers
An algorithm for nanopipelining of RTD-based circuits and architectures
IEEE Transactions on Nanotechnology
An efficient heuristic to identify threshold logic functions
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimizing the number of delay buffers in the synchronization of pipelined systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identification of Threshold Functions and Synthesis of Threshold Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Threshold logic gates allow for complex multiinput functions to be implemented using a single gate thereby reducing the power and area of a circuit. Clocked threshold gates are nanopipelined to increase network throughput. It is shown that synthesis methods that do not consider the synchronization of the nanopipeline can produce an enormous amount of buffers. The proposed algorithm synthesizes a Boolean network into a nanopipelined threshold logic network by minimizing not only the number of combinational clusters but also the associated buffer insertion overhead.