A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations

Authors:
Manoj Kumar Goparaju;Spyros Tragoudas
Affiliations:
Southern Illinois University Carbondale, USA;Southern Illinois University Carbondale, USA
Venue:
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Year:
2007

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Abstract

Threshold Logic Gates (TLG) are prone to manufacturing defects that impact weight values which inadvertently affect the functionality of the gate. A method is presented for the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extend. A novel solution is presented for the problem of identifying a fault tolerant k-input TLG for any value of k.