A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks

Authors:
Manoj Kumar Goparaju;Ashok Kumar Palaniswamy;Spyros Tragoudas
Affiliations:
-;-;-
Venue:
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Year:
2008

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Abstract

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures ...