Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Current-Mode Threshold Logic Gates
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Decomposition based approach for synthesis of multi-level threshold logic circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Threshold network synthesis and optimization and its application to nanotechnologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identification of Threshold Functions and Synthesis of Threshold Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.