Automated mapping for reconfigurable single-electron transistor arrays
Proceedings of the 48th Design Automation Conference
Journal of Nanomaterials - Special issue on 1D Nanomaterials 2011
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
Proceedings of the Conference on Design, Automation and Test in Europe
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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We propose a novel binary decision diagram (BDD) based reconfigurable logic architecture based on Split-Gate quantum nanodots using III-V compound semiconductor-based quantum wells. While BDD based quantum devices architectures have already been demonstrated to be attractive for achieving ultra-low power operation, our design provides the ability to reconfigure the functionality of the logic architecture. This work proposes device and architectural innovations to support such reconfiguration. At the device level, a unique programmability feature is incorporated in our proposed nanodot devices which can operate in 3 distinct operation modes: a) active b) open and c) short mode based on the split gate bias voltages and enable functional reconfiguration. At the architectural level, we address programmability and design fabric issues involved with mapping BDD’s into a reconfigurable architecture. By mapping a set of logic circuits, we demonstrate that our underlying device and architectural structure is flexible to support different functions.