Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Reconfigurable BDD based quantum circuits
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Multicore Processors and Systems
Multicore Processors and Systems
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On reconfigurable single-electron transistor arrays synthesis using reordering techniques
Proceedings of the Conference on Design, Automation and Test in Europe
Sensitization criterion for threshold logic circuits and its application
Proceedings of the International Conference on Computer-Aided Design
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Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automated synthesis tool for the device. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks.