On reconfigurable single-electron transistor arrays synthesis using reordering techniques

Authors:
Chang-En Chiang;Li-Fu Tang;Chun-Yao Wang;Ching-Yi Huang;Yung-Chih Chen;Suman Datta;Vijaykrishnan Narayanan
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;Yuan Ze University, Chung Li, Taiwan, R.O.C.;The Pennsylvania State University, PA;The Pennsylvania State University, PA
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 3
Cited 1

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Reconfigurable BDD based quantum circuits

NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
Automated mapping for reconfigurable single-electron transistor arrays

Proceedings of the 48th Design Automation Conference

Sensitization criterion for threshold logic circuits and its application

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power consumption has become one of the primary challenges in meeting Moore's law. Fortunately, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption during operation. An automated mapping approach for the SET architecture has been proposed recently for facilitating design realization. In this paper, we propose an enhanced approach consisting of variable reordering, product term reordering, and mapping constraint relaxation techniques to minimizing the area of mapped SET arrays. The experimental results show that our enhanced approach, on average, saves 40% in area and 17% in mapping time compared to the state-of-the-art approach for a set of MCNC and IWLS 2005 benchmarks.