A Linear Threshold Gate Implementation in Single Electron Technology

Authors:
Casper Lageweg;Sorin Cotofana;Stamatis Vassiliadis
Affiliations:
-;-;-
Venue:
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Year:
2001

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Abstract

Abstract: In this paper we focus on the design of threshold logic functions in Single Electron Tunneling (SET) technology, using the tunnel junction's specific behavior, i.e., the ability to control the transport of individual electrons. We introduce a novel design of an n-input linear threshold gate which can accommodate both positive and negative weights and built-in signal amplification, using 1 tunnel junction and n + 2 true capacitors. As an example we present a 4-input threshold gate with both positive and negative weights.