A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

Authors:
Sandeep Dechu;Manoj Kumar Goparaju;Spyros Tragoudas
Affiliations:
Southern Illinois University Carbondale, USA;Southern Illinois University Carbondale, USA;Southern Illinois University Carbondale, USA
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

Citing 0
Cited 1

A fault tolerant threshold logic gate design

ICC'09 Proceedings of the 13th WSEAS international conference on Circuits

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents simulations of 3 different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level ...