Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Automatic control systems (5th ed.)
Automatic control systems (5th ed.)
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Generation for Ground Bounce in Internal Logic Circuitry
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
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Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13 &mgr;m technology such noise in local interconnects embedded in combinational logic can exceed the threshold voltage. We show the impact of such noise on different kinds of circuits. The magnitude of this noise can increase due to process variations. We present an algorithm for generating vectors for validation and manufacturing test to detect logic-value errors caused by inductance induced oscillation. To faciliate the vector generation method, we have derived analytical expressions, as functions of rise and fall times for (i) the magnitude of overshoots and undershoots, and (ii) the settling time, i.e., the time required for the circuit response to settle to a bound close to the final value.