IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Comparative analysis of conventional and statistical design techniques
Proceedings of the 44th annual Design Automation Conference
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Exact distribution of the max/min of two Gaussian random variables
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing variability in chip-multiprocessors with adaptive body biasing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A lower bound computation method for evaluation of statistical design techniques
Proceedings of the International Conference on Computer-Aided Design
Exploiting process variability in voltage/frequency control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Inherent process device variations and fluctuations during manufacturing have a large impact on the microprocessor maximum clock frequency and total leakage power. These fluctuations have a statistical distribution that calls for usage of statistical methods for frequency and leakage analysis. This paper presents a simple technique for accurate estimation of product high-level (Full Chip) parameters such as the maximum frequency (FMAX) distribution and the total leakage (ISB). Moreover, this technique can grade critical paths by their failure probability and perform what-if analysis to estimate FMAX after fixing specific speed paths. Using our FMAX/ISB prediction, we show good correlation with silicon measurements from a production microprocessor.