Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Authors:
Ruijing Shen;Sheldon X. -D. Tan;Ning Mi;Yici Cai
Affiliations:
Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
Venue:
Integration, the VLSI Journal
Year:
2010

Citing 20
Cited 3

Stochastic finite elements: a spectral approach

Stochastic finite elements: a spectral approach
Numerical recipes in C (2nd ed.): the art of scientific computing

Numerical recipes in C (2nd ed.): the art of scientific computing
A first course in the numerical analysis of differential equations

A first course in the numerical analysis of differential equations
Technology and design challenges for low power and high performance

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations

Proceedings of the 2002 international symposium on Low power electronics and design
The Wiener--Askey Polynomial Chaos for Stochastic Differential Equations

SIAM Journal on Scientific Computing
Modeling uncertainty in flow simulations via generalized polynomial chaos

Journal of Computational Physics
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

Proceedings of the 2003 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and reliability challenges in nanometer technologies

Proceedings of the 41st annual Design Automation Conference
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Full-chip analysis of leakage power under process variations, including spatial correlations

Proceedings of the 42nd annual Design Automation Conference
Stochastic analysis of interconnect performance in the presence of process variations

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS)

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

Proceedings of the 43rd annual Design Automation Conference
Modeling and estimation of full-chip leakage current considering within-die correlation

Proceedings of the 44th annual Design Automation Conference
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation

Proceedings of the 47th Design Automation Conference
System-level leakage variability mitigation for MPSoC platforms using body-bias islands

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient method for analyzing on-chip thermal reliability considering process variations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method employs the orthogonal polynomials to represent the variational gate-level leakages in a closed form first, which is generated by a fast multi-dimensional Gaussian quadrature method. The total leakage currents then are computed by simply summing up the resulting orthogonal polynomials (their coefficients). Unlike many existing approaches, no grid-based partitioning and approximation are required. Instead, the spatial correlations are naturally handled by orthogonal decompositions. The proposed method is very efficient and it becomes linear in the presence of strong spatial correlations. Experimental results show that the proposed method is about 16x faster than the recently proposed method (Chang and Sapatnekar, 2005 [1]) with constant better accuracy.