Timing analysis with compact variation-aware standard cell models
Integration, the VLSI Journal
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
Workload-adaptive process tuning strategy for power-efficient multi-core processors
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A dynamic method for efficient random mismatch characterization of standard cells
Proceedings of the International Conference on Computer-Aided Design
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
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In this paper, we present a unified approach for the statistical timing and leakage analysis of circuits in the presence of intradie variations. The intradie variations in device parameters are modeled as a spatial stochastic process with a given covariance function. The covariance function is used to construct a Karhunen-Loeve expansion of the spatial process. This leads to representing the various parameters of all components on the chip in terms of a common set of abstract random variables. The leakage and propagation delay of each gate are represented as quadratic polynomials (QPs), which are elements of a vector space whose bases are multivariate quadratic orthogonal polynomials of the device parameters. In the case of signal arrival times, we describe an efficient method to propagate the QPs through the circuit to obtain a QP representation of the signal arrival times at the primary outputs. The analysis is extended to include sequential components so that flip-flop parameters and clock arrival times can be treated as random variables. This allows efficient estimation of the timing yield of the circuit. We show how a similar representation of QP can be used to model leakage of gates and develop an efficient method to compute a QP representation of the total chip leakage. The proposed techniques and quadratic models were exercised on ISCAS89 benchmark circuits and compared with Monte Carlo (MC) simulations. The results show that the techniques are very accurate and several orders of magnitude faster than MC simulation.