Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip analysis of leakage power under process variations, including spatial correlations
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ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 45th annual Design Automation Conference
A probabilistic technique for full-chip leakage estimation
Proceedings of the 13th international symposium on Low power electronics and design
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 46th Annual Design Automation Conference
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
Integration, the VLSI Journal
Proceedings of the 2009 International Conference on Computer-Aided Design
A linear statistical analysis for full-chip leakage power with spatial correlation
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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Full-chip leakage analysis for 65nm CMOS technology and beyond
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power yield analysis under process and temperature variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and within-die process variations, and taking into account the spatial correlation due to within-die variations. Our model uses a "random gate" concept to capture high-level characteristics of a candidate chip design, which are sufficient to determine its leakage. We show empirically that, for large gate count, the set of all chip designs that share the same high level characteristics have approximately the same leakage, with very small error. Therefore, our model can be used as either an early or a late estimator of leakage, with high accuracy. In its simplest form, we show that full-chip leakage estimation reduces to finding the area under a scaled version of the within-die channel length auto-correlation function, which can be done in constant time.