Kendall's advanced theory of statistics
Kendall's advanced theory of statistics
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 international symposium on Low power electronics and design
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Modeling and estimation of full-chip leakage current considering within-die correlation
Proceedings of the 44th annual Design Automation Conference
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Coping with Variations through System-Level Design
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and verification of power grids considering process-induced leakage-current variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design-Specific Optimization Considering Supply and Threshold Voltage Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the IR drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temperature and Vdd, the power yield is estimated for a chip. This helps check the robustness of the circuits early in the design process. The experimental results on the ISCAS 89 benchmarks indicate a significant yield loss, if the statistical measures of the temperature and voltage drop are ignored. Monte Carlo simulations verify the accuracy of the developed methodology.