Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Computational Methods for Inverse Problems
Computational Methods for Inverse Problems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Many-core design from a thermal perspective
Proceedings of the 45th annual Design Automation Conference
Thermal and power characterization of field-programmable gate arrays
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Improved post-silicon power modeling using AC lock-in techniques
Proceedings of the 48th Design Automation Conference
Agent-based thermal management using real-time I/O communication relocation for 3D many-cores
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PowerField: a transient temperature-to-power technique based on Markov random field theory
Proceedings of the 49th Annual Design Automation Conference
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Post-silicon power mapping techniques for integrated circuits
Integration, the VLSI Journal
A power-driven thermal sensor placement algorithm for dynamic thermal management
Proceedings of the Conference on Design, Automation and Test in Europe
High-sensitivity hardware trojan detection using multimodal characterization
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime power estimator calibration for high-performance microprocessors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Compact thermal modeling for packaged microprocessor design with practical power maps
Integration, the VLSI Journal
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Design-time power analysis is one of the most critical tasks conducted by chip architects and circuit designers. While computer-aided power analysis tools can provide power consumption estimates for various circuit blocks, these estimates can substantially deviate from the actual power consumption of working silicon chips. We propose a novel methodology that provides accurate, detailed post-silicon spatial power estimates using the thermal infrared emissions from the backside of silicon die. We theoretically and empirically demonstrate the inherent difficulties in thermal to power inversion. These difficulties arise from measurement errors and from the inherent spatial low-pass filtering associated with heat diffusion. To address these difficulties we propose new techniques from regularization theory to invert temperature to power. Furthermore, we propose new techniques to compute the emissivities and conductances required for any infrared to power inversion method. To verify our results, a programmable circuit of micro heaters is implemented to create any desired power pattern. The thermal emissions of different known injected power patterns are captured using a state-of-the-art infrared camera, and then our characterization techniques are applied to invert the thermal emissions to power. The estimated power patterns are validated against the injected power patterns to demonstrate the accuracy of our methodology.