Power estimation techniques for integrated circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Many-core design from a thermal perspective
Proceedings of the 45th annual Design Automation Conference
Post-silicon power characterization using thermal infrared emissions
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Focal-plane-arrays and CMOS readout techniques of infrared imaging systems
IEEE Transactions on Circuits and Systems for Video Technology
PowerField: a transient temperature-to-power technique based on Markov random field theory
Proceedings of the 49th Annual Design Automation Conference
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
A power-driven thermal sensor placement algorithm for dynamic thermal management
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime power estimator calibration for high-performance microprocessors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The objective of power modeling is to estimate the power consumption of integrated circuits under different workloads and variabilities. Post-silicon power modeling is an essential step for design validation and for building trustable pre-silicon power models and analyses. One popular approach for devising post-silicon power estimates is to translate the thermal emissions from the backside of the die into power estimates. Such approach faces a major physical challenge arising from spatial heat diffusion which blurs the resultant thermal images. The objective of this paper is to improve post-silicon power mapping by utilizing lock-in thermography techniques where AC signals, rather than DC signals, are used to excite the circuit blocks. We prove and demonstrate that using AC excitation sources reduces the extent of spatial heat diffusion. We devise a lock-in based thermal to power inversion methodology that maps spatial power consumption on a real chip. Using a custom test chip, we are to able to scientifically quantify and validate the improvements in power mapping attained from the proposed techniques. We show that our technique reduces the power mapping errors by more than half.