Modeling and Analysis of Parametric Yield under Power and Performance Constraints

Authors:
Rajeev R. Rao;David Blaauw;Dennis Sylvester;Anirudh Devgan
Affiliations:
University of Michigan, Ann Arbor;University of Michigan, Ann Arbor;University of Michigan, Ann Arbor;Magma Design Automation
Venue:
IEEE Design & Test
Year:
2005

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Abstract

Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.