Proceedings of the 2003 international symposium on Low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Static timing: back to our roots
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical yield prediction considering leakage/performance correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Process variation is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured chips do not satisfy timing or power constraints. On the other hand, both chip performance and chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky chips into good ones by adjusting their supply voltage. This technique is called voltage binning [4]. All the manufactured chips are divided into groups (bins) and each group is assigned its individual supply voltage. This paper proposes a statistical technique of yield computation for different voltage binning schemes using results of statistical timing and variational power analysis. The paper formulates and solves the problem of computing optimal supply voltages for a given binning scheme.