On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis of non-uniform temperature-dependent interconnect performance in high performance ICs
Proceedings of the 38th annual Design Automation Conference
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical method for the analysis of interconnects delay in submicrometer layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The paper provides a compact but accurate electro-thermal model of a long wiring on-chip interconnect embedded in the complex layout of a ULSI digital circuit. The proposed technique takes into account both the effect of temperature gradients over the chip substrate and the interconnect self-heating due to current flow. The proposed compact model is well suited to be interfaced with commercially available CAD tools employed for interconnect parasitic extraction and signal integrity verification. The paper also investigates the electro-thermal effects that arise in a long wiring on-chip interconnect in which current flow is dominated by displacement currents and thus is not uniform along the line.