HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Performance implications of single thread migration on a chip multi-core
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
A study of thread migration in temperature-constrained multicores
ACM Transactions on Architecture and Code Optimization (TACO)
Throughput of multi-core processors under thermal constraints
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding the Thermal Implications of Multi-Core Architectures
IEEE Transactions on Parallel and Distributed Systems
Dynamic thermal management via architectural adaptation
Proceedings of the 46th Annual Design Automation Conference
Fast and accurate thermal modeling and simulation of manycore processors and workloads
Microelectronics Journal
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Migrating threads away from the hot cores in a multicore processor allows them to operate at up to higher speeds. While this technique has already attracted a lot of research effort, the majority of thread migration studies are simulation-based. Although they are valuable for micro-architectural level optimization, they require prohibitively long simulation times, and hence have limited value for early design space exploration. We derive closed form expressions for the steady-state throughput of a multicore processor that employs thread migration and throttling for thermal management. These expressions can be evaluated under a millisecond (vs days for cycle-accurate simulation), and allow designers greater flexibility in evaluating the trade-offs involved in implementing thread migration on-chip. We also developed a system-level power/thermal simulator that we used to validate the analytical results.