Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
The Impact of Technology Scaling on Lifetime Reliability
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Temperature-aware resource allocation and binding in high-level synthesis
Proceedings of the 42nd annual Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
HW-SW emulation framework for temperature-aware design in MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal balancing policy for streaming computing on multiprocessor architectures
Proceedings of the conference on Design, automation and test in Europe
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Full Length Article: 3D thermal-aware floorplanner using a MILP approximation
Microprocessors & Microsystems
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Thermal effects are becoming increasingly important in today's sub-micron technologies. Thermal issues affect the performance, the reliability and the cooling costs of integrated systems. High peak temperatures are of major concern in modern 3D designs, where the stacking of multiple layers leads to higher power densities. Therefore, the integration of the thermal-aware design during the initial phases of the design can reduce the cost and the time-to-market of the resulting product. An efficient floorplanning in terms of thermal effects will reduce the appearance of critical hotspots and will spread heat across the chip area. This paper analyzes the thermal distribution of 3D multicore architectures and provides a motivation for the need of a thermal-aware floorplanner for such architectures.