IEEE Transactions on Computers
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Proceedings of the 2004 international symposium on Physical design
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Proceedings of the 41st annual Design Automation Conference
Design and implementation of the POWER5™ microprocessor
Proceedings of the 41st annual Design Automation Conference
A First-Order Superscalar Processor Model
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Interconnect-driven floorplanning by searching alternative packings
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Approximation algorithms for combinatorial problems
Journal of Computer and System Sciences
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated floorplanning with buffer/channel insertion for bus-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous floor plan and buffer-block optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput-driven floorplanning with wire pipelining
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting local logic structures to optimize multi-core SoC floorplanning
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Microarchitecture configurations and floorplanning are keys to boost throughput, and they are strongly related. In this paper, we propose a new method to optimize them simultaneously. We first concentrate on floorplanning under given microarchitecture configurations. In addition to the objectives of conventional floorplanning methods, we minimize the throughput degradation caused by pipelined global interconnects based on efficient yet accurate models for microarchitecture throughput over pipeline stages of global interconnects. Our results show that an accurate trajectory piecewise-linear (TPWL) model incurs more offline setup time to obtain 13% better throughput than a rough access ratio-based model, and both models lead to much better throughput (up to 64% higher) compared with conventional floorplanning methods. We then build a unified throughput model parameterized for pipelined global interconnects and microarchitecture configurations based on the TPWL method and apply this model to efficiently explore over one million microarchitecture configurations and corresponding floorplan variations. We obtain microarchitecture configurations and floorplans with throughput 26.9% better than manually chosen microarchitecture followed by automatic floorplanning in a very recent paper.