The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Modeling Superscalar Processors via Statistical Simulation
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Microarchitecture evaluation with physical planning
Proceedings of the 40th annual Design Automation Conference
SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
Proceedings of the 30th annual international symposium on Computer architecture
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Approximation algorithms for combinatorial problems
Journal of Computer and System Sciences
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Proceedings of the 41st annual Design Automation Conference
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Proceedings of the 2005 international symposium on Physical design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Microarchitecture evaluation with floorplanning and interconnect pipelining
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 2006 international symposium on Low power electronics and design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Microarchitecture configurations and floorplanning co-optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature aware microprocessor floorplanning considering application dependent power load
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Micro-architecture performance estimation by formula
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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Interconnect pipelining has a great impact on system performance, but has not been considered by automatic floorplanning. Consid-ering interconnect pipelining, we study the floorplanning optimiza-tion problem to minimize system CPI (cycles per instruction) and in turn maximize system performance. We develop an efficient table-based model called trajectory piece-wise linear (TPWL) model to estimate CPI with interconnect pipelining. Experiments show that the TPWL model differs from cycle-accurate simulations by less than 3.0%. We integrate this model with a simulated-annealing based floorplan optimization to obtain CPI-aware floorplanning. Compared to the conventional floorplanning to minimize area and wire length, our CPI-aware floorplanning can reduce CPI by up to 28.6% with a small area overhead of 5.69% under 100nm technol-ogy and obtain better results under 70nm technology. To the best of our knowledge, this paper is the first in-depth study on floorplan-ning optimization with consideration of interconnect pipelining.