Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Interconnect characteristics of 2.5-D system integration scheme
Proceedings of the 2001 international symposium on Physical design
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design of mixed-signal systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
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System-on-package (SOP) is a viable alternative to system-onchip (SOC) for meeting the rigorous requirements of today's mixed-signal system integration. Thermal integrity is arguably the most crucial issue in three-dimensional (3-D) SOP due to the compact nature of the 3-D integration. In addition, the power supply noise issue becomes more serious as the supply voltage continues to decrease while the number of active devices consuming power increases. We propose a 3-D module and decap (decoupling capacitance) placement algorithm that evenly distributes the thermal profile and reduces the power supply noise. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both maximum temperature and decap amount with only small increase in area, wirelength, and runtime.