Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Before VLSI design starts, it is strategically important to do product planning for targeted market segments that need specific applications, and to optimally reuse at different levels to save design and silicon costs with shorter time-to-market schedule. Conventional ASIC or SoC design floorplan usually targets for one single product; and, high efforts in re-floorplan and re-convergence for different products are still required if there is no pre-design stage multi-product planning. Therefore, the problem of designing floorplans at product or market planning stage that simultaneously optimizes multiple products, or Multi-product Floorplanning, is introduced. To the best of our knowledge, this is the first work in literature that addresses this newly emerged and financially important problem. We start with the necessary number of basic functional blocks to accommodate all the products, and pack them using a simulated annealing (SA) based floorplanner that can easily incorporate other costs (e.g., product finance weights). Given a candidate floorplan, we provide both an O(n3) exact algorithm and a O(n) greedy heuristic to identify the Minimum Feasible Region for each product, where n is the number of basic blocks in this floorplan. These identification procedures are integrated into the SA framework to generate a floorplan that favors the configurable multi-product design. The effectiveness of our approach is validated by promising results on several data sets derived from industrial test cases.