Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A high efficiency full-chip thermal simulation algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect thermal modeling for accurate simulation of circuit timing and reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring
Proceedings of the 49th Annual Design Automation Conference
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the product of Green's function and power density integrated over space. The correlation coefficient between thermal signature and temperature is shown to be quite high, more than 0.7 in many examples. A floorplanner that uses thermal signature is constructed and assessed using real design examples in 32-nm technology. It produces a floorplan whose maximum temperature is 11.4°C smaller than that of standard floorplan, on average, in reasonable amount of runtime.