Proceedings of the 2001 international symposium on Physical design
Coupled analysis of electromigration reliability and performance in ULSI signal nets
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Microelectronic Engineering
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Clock Distribution Network Optimization under Self-Heating and Timing Constraints
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An electromigration and thermal model of power wires for a priori high-level reliability prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Adaptive chip-package thermal analysis for synthesis and design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 International Conference on Computer-Aided Design
An accurate interconnect thermal model using equivalent transmission line circuit
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal signature: a simple yet accurate thermal index for floorplan optimization
Proceedings of the 48th Design Automation Conference
On-chip thermal modeling based on SPICE simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Analog Integrated Circuits and Signal Processing
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We apply three-dimensional finite element analysis to study the thermal coupling between nearby interconnects. We find that the temperature rise in current-carrying lines is significantly influenced by a dense array of lines in a nearby metal level. In contrast, thermal coupling between just two neighboring parallel lines is insignificant for most geometries. Design rules for average root-mean-square current density are provided for specific geometries given the requirement that the interconnect temperature be no more than 5°C above the substrate temperature. Semi-empirical formulae for coupling effects are presented based on the numerical results. A procedure is proposed to implement the formulae in computer-aided design tools