On-chip thermal modeling based on SPICE simulation

Authors:
Wei Liu;Andrea Calimera;Alberto Nannarelli;Enrico Macii;Massimo Poncino
Affiliations:
Technical University of Denmark, Denmark;Politecnico di Torino, Italy;Technical University of Denmark, Denmark;Politecnico di Torino, Italy;Politecnico di Torino, Italy
Venue:
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

With technology scaled to deep submicron regime, temperature and temperature gradient have emerged as important design criteria. Elevated temperatures, spatial and temporal temperature variations and on-chip hotspot not only affect timing in both transistors and interconnects but also degrade circuit reliability. A SPICE simulation based thermal modeling method is proposed in this paper. Experiments on a set of tests show the correlations between functional and spatial hotspots in a circuit implemented in STM 65nm technologies.