IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A high efficiency full-chip thermal simulation algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-chip thermal modeling based on SPICE simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In this paper, we present a method to efficiently identify the onchip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in early chip design phase, for which a large number of design iterations is needed and simulation efficiency is much required.