Convexification and Global Optimization in Continuous And
Convexification and Global Optimization in Continuous And
IPRAIL: intellectual property reuse-based analog IC layout automation
Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Mathematical Programming: Series A and B
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
An automated design tool for analog layouts
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
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Performance of analog integrated circuits is highly sensitive to layout parasitics. This paper presents an improved template-based algorithm that automatically conducts performance-constrained parasitic-aware retargeting and optimization of analog layouts. In order to achieve desired circuit performance, performance sensitivities with respect to layout parasitics are first determined. Then the algorithm applies a piecewise-sensitivity model to control parasitic-related layout geometries by directly constructing a set of performance constraints subject to maximum performance deviation due to parasitics. The formulated problem is finally solved using graph-based techniques combined with mixed-integer nonlinear programming. The proposed method has been incorporated into a parasitic-aware automatic layout optimization and retargeting tool. It has been demonstrated to be effective and efficient especially when adapting layout design for new technologies or updated specifications.