Constraint generation for routing analog circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Generalized constraint generation for analog circuit design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General AC constraint transformation for analog ICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
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In a constraint-driven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to non-deterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with non-deterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are a well-defined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design.