Generation of performance sensitivities for analog cell layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A constraint based approach to automatic design of analog cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
EURO-DAC '92 Proceedings of the conference on European design automation
Simultaneous placement and module optimization of analog IC's
DAC '94 Proceedings of the 31st annual Design Automation Conference
Use of sensitivities and generalized substrate models in mixed-signal IC design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Generalized constraint generation in the presence of non-deterministic parasitics
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A video driver system designed using a top-down, constraint-driven methodology
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Generalized constraint generation for analog circuit design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
System-level routing of mixed-signal ASICs in WREN
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
HERO: hierarchical EMC-constrained routing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Techniques for Synthesis of Analog Integrated Circuits
IEEE Design & Test
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
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An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.