Constraint generation for routing analog circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
General AC constraint transformation for analog ICs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A benchmark suite for substrate analysis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deterministic approaches to analog performance space exploration (PSE)
Proceedings of the 42nd annual Design Automation Conference
Robust system level design with analog platforms
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
A platform-based methodology for system-level mixed-signal design
EURASIP Journal on Embedded Systems - Special issue on design methodologies and innovative architectures for mixed-signal embedded systems
Hi-index | 0.00 |
To accelerate the design cycle for analog and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. The key idea of the proposed methodology is hierarchically propagating constraints from performance specifications to layout. Consequently, it is essential to provide the necessary tools and techniques enabling the efficient constraint propagation. To illustrate the applicability of the proposed methodology to the design of larger systems, we present in this paper the complete design flow for a video driver system. Critical advantages of the methodology illustrated with this design example include avoiding costly low level re-designs and getting working silicon parts from the first run. Following our approach, a jitter constraint is imposed at the system level and then is propagated hierarchically to the circuit blocks and layout, using behavioral modeling and simulation. Experimental results are presented from working fabricated parts.