Sequence-pair based placement method for hard/soft/pre-placed modules
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Floorplan sizing by linear programming approximation
Proceedings of the 37th Annual Design Automation Conference
Slicing tree is a complete floorplan representation
Proceedings of the conference on Design, automation and test in Europe
Convex Optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An Integrated Layout-Synthesis Approach for Analog ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Template coding with LDS and applications of LDS in EDA
Analog Integrated Circuits and Signal Processing
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A methodology to optimize the area of a fixed non-slicing floorplan is presented in this paper. Areas of transistors, capacitors and resistors are formulated as convex functions and area is minimized by solving a sequence of convex problems. The methodology is practical even with many components and variants. Moreover symmetry constraints are satisfied during optimization.