Analog placement based on novel symmetry-island formulation
Proceedings of the 44th annual Design Automation Conference
Analog placement based on hierarchical module clustering
Proceedings of the 45th annual Design Automation Conference
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Eye Diagram Construction and Analysis in Digital Phosphor Oscilloscope
ICICTA '10 Proceedings of the 2010 International Conference on Intelligent Computation Technology and Automation - Volume 02
Fast analog layout prototyping for nanometer design migration
Proceedings of the International Conference on Computer-Aided Design
Practical placement and routing techniques for analog circuit designs
Proceedings of the International Conference on Computer-Aided Design
Multilevel symmetry-constraint generation for retargeting large analog layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area routing for analog layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient analog layout prototyping by layout reuse with routing preservation
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we present a novel configurable analog routing methodology for more efficient analog layout automation. By the help of OpenAccess constraint group format, the technology process rules and analog layout design intention/constraints are unified through schematic level to layout level. In contrast to self-defined constraint format in prior arts, proposed approach manipulates the analog routing characteristic based on the unified constraints. In different circuit hierarchies defined by circuit designers or extracted by existing placement, the hierarchical structure is formed as specific analog layout constraint groups. This work efficiently facilitates analog routing strategy which honors the specific analog constraints. By practicing on an analog functional block of tsmc 40nm SoC design which guarantees to be legalized and satisfies required analog constraints by DRC/LVS and post-layout simulation respectively, the results in wire matching for signal integrity show that the different routing priority generated by our approach can have significant performance impact.